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LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 1 of 48 LUPA-1300 1.3 m pixel high speed cmos image sensor datasheet
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 2 of 48 document history record issue date description of changes 2.1 april, 2003 first draft. 3.0 march, 2004 updated timing diagrams updated layout updated package drawings disclaimer soldering and handling conditions updated specifications 3.1 december, 2004 added equiva lent cypress part numbers, ordering information. added cypress document # 38-05711 rev ** in the document footer.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 3 of 48 t able of contents 1 preamble ....................................................................................................................... .......... 5 1.1 o verview .............................................................................................................................. 5 1.2 m ain features ...................................................................................................................... 5 1.3 p art n umber ........................................................................................................................ 6 2 specifications ................................................................................................................. ..... 7 2.1 g eneral specifications ....................................................................................................... 7 2.2 e lectro - optical characteristics ..................................................................................... 7 2.2.1 overview ......................................................................................................................... 7 2.2.2 features and general specifications .............................................................................. 8 2.2.3 spectral response curve ................................................................................................. 9 2.2.4 photo-voltaic response curve ....................................................................................... 10 2.3 e lectrical specifications ................................................................................................ 11 2.3.1 absolute maximum ratings .......................................................................................... 11 2.3.2 recommended operating conditions ........................................................................... 11 3 sensor architecture .................................................................................................... 13 3.1 p ixel architecture ............................................................................................................ 14 3.2 c olumn readout amplifiers ............................................................................................. 15 3.3 o utput amplifiers .............................................................................................................. 16 3.4 f rame rate and windowing .............................................................................................. 17 3.4.1 frame rate calculation ................................................................................................ 17 3.4.2 x-y addressing and windowing ................................................................................... 17 3.5 t emperature reference circuits .................................................................................... 18 3.5.1 temperature diode ....................................................................................................... 18 3.5.2 temperature module .................................................................................................... 18 3.6 s ynchronous shutter ....................................................................................................... 20 3.7 n on - destructive readout (ndr).................................................................................... 21 3.8 o peration and signaling .................................................................................................. 21 3.8.1 power supplies and grounds ........................................................................................ 22 3.8.2 biasing and analog signals ......................................................................................... 24 3.8.3 pixel array signals ....................................................................................................... 24 3.8.4 digital signals .............................................................................................................. 26 3.8.5 test signals ................................................................................................................... 27 4 timing ......................................................................................................................... ............. 28 4.1 t iming of the pixel array ................................................................................................. 28 4.2 r eadout of the pixel array ............................................................................................. 29 4.2.1 reduced row overhead time timing .......................................................................... 31 4.3 t iming of the s erial p arallel i nterface (spi)............................................................. 33 5 pin configuration ............ ............................................................................................... 34 6 pad positioning and packaging . ............................................................................. 39 6.1 p ackage ............................................................................................................................... 39 6.2 p ackage and die ................................................................................................................. 40 6.3 c olor filter ....................................................................................................................... 41 6.4 g lass transmittance ........................................................................................................ 42 6.4.1 monochrome ................................................................................................................ 42 6.4.2 color ............................................................................................................................. 42 6.5 h andling and s torage precautions ............................................................................... 43
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 4 of 48 6.6 h andling precautions ...................................................................................................... 43 6.7 s torage conditions ........................................................................................................... 44 7 ordering information ................................................................................................. 44 8 application notes & faq.............................................................................................. 45 appendix a: LUPA-1300 evaluation kit... ................ ............ ............ ............. ............ ....... 47
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 5 of 48 1 preamble 1.1 overview this document describes the interfacing and the driving of the image sensor lupa1300, which is a 1280 by 1024 cmos pixel array working at 450 frames/sec. the sensor is an active pixel sensor with synchronous shutter. the pixel size is 14 * 14 m and the sensor is designed to achi eve a fame rate of 450 frames/sec at full resolution. this high frame rate can be achieved by 16 parallel output amplifiers each working at 40mhz pixel rate. the readout speed can be boosted by mean s of windowed region of interest (roi) readout. high dynamic range scenes can be captured using the double slope functionality. the sensor uses a 3-wire serial-parallel (spi) interface. it is housed in a 145-pin ceramic pga package. in the following sections th e different modules of the image sensor are discussed more into detail. this datasheet allows th e user to develop a camera-system based on the described timing and interfacing. 1.2 main features the main features of the image sensor are identified as: ? sxga resolution: 1280 x 1024 active pixels. ? 14 m 2 square pixels (based on the high- fill factor active pixel sensor technology of fillfactory (us pa tent no. 6,225,670 and others)). ? pixel rate of 40 mhz us ing 16 parallel outputs. ? random programmable windowing. ? dual slope integration possible ? 145-pin pga package ? peak qe x ff of 15%. ? optical format: 1,43? (17.9 mm x 14.3 mm) ? optical dynamic range: 62 db (1330:1) in single slope operation and 80?100 db in double slope operation. ? 16 parallel analog output amplifiers. ? synchronous pipelined shutter. ? processing is done in a cmos 0.50 m triple metal process.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 6 of 48 1.3 part number name package monochrome / color LUPA-1300-m cyil1sm1300aa-gbc (preliminary) 145-pins pga package. monochrome. LUPA-1300-c cyil1sc1300aa-gac (preliminary) 145-pins pga package. rgb bayer pattern.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 7 of 48 2 specifications 2.1 general specifications parameter specification remarks pixel architecture 6t-pixel based on the high- fill factor active pixel sensor technology of fillfactory pixel size 14 m x 14 m resolution 1280 x1024 the resolution and pixel size results in a 17.9 mm x 14.3 mm optical active area. pixel rate 640 mhz using a 20 mhz system clock and 16 parallel outputs. shutter type pipelined snapshot shutter full snapshot shutter with variable integration time full frame rate 450 frames/second frame rate in crease possible with roi read out and/or sub sampling. package pin grid array 145 pins table 1: general specificat ions of the lupa sensor 2.2 electro-optical characteristics 2.2.1 overview parameter specification remarks fpn <2 % rms <10 % p/p. prnu 20 % rms half saturation. conversion gain 16 uv/electron output signal amplitude 1v unity gain. saturation charge 62.500 e- is more then 60.000 (=1v/16uv/e-) due to non- linearity in saturated region. 1500 v.m2/w.s average white light. 8.33 v/lux.s visible band only (180 lx = 1 w/m2). sensitivity 21.43 v/lux.s visible + nir (70 lx = 1 w/m2). fill factor 50% 100%-metal and polycide coverage. peak qe * ff peak sr * ff 15% 0.08 a/w see spectral response curve. mtf x: 67 % y: 66% @ nyquist temporal noise 45e- dark environment, measured at t=21 c.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 8 of 48 s/n ratio 1330 1330 = 60000:45 = 62 db. spectral sensitivity range 400 ? 1000 nm parasitic light sensitivity < 0.5 % i.e. sensitivity of the storage node compared to the sensitivity of photodiode power dissipation 900 mwatt typical. output impedance 200-300 ohms typical table 2: electrical-optical specifi cations of the LUPA-1300 sensor 2.2.2 features and general specifications feature specification/description electronic shutter type synchronous pipelined shutter with variable integration time. windowing (roi) programmable via spi. read out sequence progressive scan. extended dynamic range double slope extended dynamic range. x clock 20 mhz (pixel ra te of 40 mhz) number of outputs 16. supply voltage vdd image core supply: range from 3v to 6 v. analog supply: nominal 5 v. digital: nominal 5 v. logic levels 5v (digital supply) operational temperature range 0c to 60c, with degradation of dark current. package 145-pins pin grid array (pga). table 3: features and general specifications
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 9 of 48 2.2.3 spectral response curve 0 0.02 0.04 0.06 0.08 0.1 0.12 400 500 600 700 800 900 1000 wavelength (nm) response (a/w) qe=10% qe=15% qe= 20% LUPA-1300 figure 1: spectral response curve figure 1 shows the spectral response characteristic. the cu rve is measured directly on the pixels. it includes effects of non-sensitive areas in the pixel, e.g. interconnection lines. the sensor is light sensitive betw een 400 and 1000 nm. the peak qe * ff is 15% approximately between 500 and 700 nm.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 10 of 48 2.2.4 photo-voltaic response curve figure 2: output voltage as a f unction of the number of electrons . as one can see from figure 2, the output si gnal ranges between 1.1 v (dark) to 0 v (saturation) and is linear until around 800mv. note that the upper part of the curve (near saturation) is actually a logarithmic response.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 11 of 48 2.3 electrical specifications 2.3.1 absolute maximum ratings symbol parameter value unit v dc dc supply voltage -0.5 to +7 v v in dc input voltage 0.5 to v dc + 0.5 v v out dc output voltage -0.5 to v dc + 0.5 v i dc current per pin; any single input or output. (see table 7 for more exceptions) 50 ma t stg storage temperature range. -40 to 100 c t l lead temperature (10 seconds soldering). 300 c table 4: absolute maximum ratings note: absolute ratings are those values be yond which damage to the device may occur. 2.3.2 recommended operating conditions symbol parameter typ unit vdda power supply column read out module. 5 v vdd power supply digital modules 5 v vddr power supply logic for drivers 5 v voo power supply output stages 5 v vres power supply reset drivers 6 v vres_ds power supply multiple slope reset driver 4.5 v vmem_h power supply memory element (high level) 6 v vmem_l power supply memory element (low level) 4.5 v vpix power supply pixel array 4.5 v vstable power supply output stages. decouples noise on the voo supply from the output signal. 5.5 v table 5: recommended operation conditions
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 12 of 48 note : 1. all parameters are characterized for dc conditions after thermal equilibrium has been established. 2. unused inputs must always be tied to an appropriate logic level, e.g. either vdd or gnd. 3. this device contains circuitry to prot ect the inputs against damage due to high static voltages or electric fields; however it is recommended that normal precautions be taken to avoid applicat ion of any voltages higher than the maximum rated voltages to this high impedance circuit.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 13 of 48 3 sensor architecture the image sensor consists of the pixel arra y, the column readout electronics, x-and y addressing, on chip drivers, the out put amplifiers and some logic. x-addressing a nalog multiplexe r column amplifiers p ixel cor e p ixel output amplifiers imager core spi interface senso r y-addressin g system clock 40 mhz 3 2 1 16 15 14 drivers for the pixel array signals control signals figure 3: architecture of the lupa sensor figure 3 shows a schematic representation of the image sensor on which the different modules are displayed. the image core is a pixel array of 1280 * 1024 pixels each of 14 *14 m2 in size. the readout is from bottom left to top right. to obtain a fram e rate of 450 frames/sec for this resolution, 16 output amplifiers each capable of driving an output capacitance of 10 pf at 40mhz are placed on the image sensor. the column readout amplifiers bring the pixe l data to the output amplifiers. the logic and the x- and y addressing controls the im age sensor so that progressive scan and windowing is possible. extra pixel array drivers are foreseen at the top of the image sensor to control the global pixel array signals.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 14 of 48 3.1 pixel architecture the active pixels allow synchronous shutter ?i .e. all pixels are illuminated during the same integration time, starting from the same moment in time. after a certain integration time, the pixels are readout se quentially. readout and integration are in parallel, which means that when the image se nsor is readout, the integration time for the next frame is ongoing. this feature re quires a memory element inside the pixel, which affects the maximum fill factor. a schematic representation of the pixel is given in figure 4. precharge reset sample row select column out vp ix mem figure 4: schematic represen tation of the synchronous pixel as used in the lupa design the signals mentioned in figure 4 are the inte rnal signals, generate d by the internal drivers, required to have the synchronous shutter feature . the photodiode is designed to obtain sensiti vity as high as possible for a dynamic range of at least 60db. consequently the photodiode capacitance is 10ff @ the output, resulting in a s/n of more than 60 db as the rms noise level is within the expectation of 45 noise electrons. the pixel was specially designed to have a very low parasitic light sensitivity (<0.5%). the pixe ls are based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others)).
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 15 of 48 3.2 column readout amplifiers the column readout amplifiers are the in terface between the pixels and the output amplifiers. the pixels in the array are se lected line by line and the pixels of the selected line are connected to the column readout amplifiers, which bring the pixel data in the correct format to the output amplifiers. to obtain a high frame rate, the complexity and the number of stages in the column readout amplifiers must be minimized, so th at the power dissipation remains as low as possible, but also to minimize the row blanking time. figure 5 is a schematic representation of the column readout structure. it consists of 2 parts. the first part is a module that reduces the row blanking time. the second part shifts the signal to the correct level for the output amplifiers and al lows multiplexing in the x-direction. from the moment that a new row is selected, the pixel data of that row is placed onto the columns of the pixel array. these columns are long lines and have a large parasitic capacitance. as the pixel is small, it is not possible to match the transistor inside the pixel, which drives this colu mn. consequently, the first module in the column readout amplifiers must solve the mismatch between the pixel driver and the large column capacitance. figure 5: schematic representation of the column readout structure. output stage column module 1 : track & hold or reference set method module 2 : signal conditioning and multiplexing x-mux sh kol n orow sel
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 16 of 48 3.3 output amplifiers 16 output amplifiers each capable of wo rking at 40mhz pixel rate are placed equidistant on the bottom of the image sensor . these output amplifiers are required to obtain a frame rate of 450 fr ames/sec. a single output stage, not only to reduce power, but also to achieve the required pixel rate is designed. figure 6 is a schematic representation of this module. figure 6: schematic representa tion of a single output stage. each output stage is designed to drive a load of 10pf at a pixel ra te of 40mhz. the load in the output stage determines this pixel rate. in case the load capacitance is less than 10pf, the load in the output stag e can increase, resulting in less power dissipation of the output stag es and consequently of the whole sensor. additionally, decreasing the load of the output stage al lows having more current available for the output stage to charge or discharge the load ca pacitance to obtain a higher pixel rate. to avoid variations on the supply voltage to be seen on the output signal, a special module to stabilize the power supply is required. this module that requires an additional supply voltage (v stable) allows variation on the supply voltage voo without being seen on the output signal. one can also choose to have a passive load of chip inst ead of the active output stage load. this deteriorates the linearity of the output stages, but decreases the power dissipation, as the dissipation in the load is external. note: the LUPA-1300 is designed to drive a capacitive load, not a resistive. when one wants to transport the output signals over long distances (more than 1 inch), make sure to place buffers on the outputs w ith high input impedances (preferably >1mohms). this is necess ary because the output impe dance of the LUPA-1300 is between 200-300 ohms typically. stabilize power supply vstable in out output stage load cload 10 pf
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 17 of 48 3.4 frame rate and windowing 3.4.1 frame rate calculation the frame period of the LUPA-1300 sensor can be calculated as follows: frame period = fot + (nr.lns* (rbt + pixel period * nr. pxs / 16) with: fot: frame overhead time = 1 us. nr. lns : number of lines read out each frame (y). nr. pxs: number of pixels read out each line (x). rbt: row blanking time = 200 ns ( nominal; can be further reduced). pixel period: clock_x period/2 (b oth rising and falling edge are active edges). - example 1 read out of the full resoluti on at nominal speed (40 mhz pixel rate): frame period = 5 us + (1024 * (200 ns + 25 ns * 1280 / 16) = 2.25 ms => 444 fps. - example 2 read out of 800x600 at nominal speed (40 mhz pixel rate): frame period = 5 us + (600 * (200 ns + 25 ns * 800 / 16) = 871 us => 1148 fps. - example 3 read out of 640x480 at nominal speed (40 mhz pixel rate): frame period = 5 us + (480 * (200 ns + 25 ns * 640 / 16) = 577 us => 1733 fps. - example 4 read out of the full resolution at nominal speed (40 mhz pixel rate) with reduced overhead time: frame period = 5 us + (1024 * (100 ns + 25 ns * 1280 / 16) = 2.15 ms => 465 fps. 3.4.2 x-y addressing and windowing the pixel array is readout by means of pr ogrammable x and y shift registers. the pixel array is scanned line-by-line and co lumn-by-column. the starting point in x and y is defined indi vidually for each register and is determined by the address downloaded by the serial ? para llel interface (spi). both re gisters work in the same way. a sync pulse that sets the address pointer to the star ting address of each register, initializes them. a clock pulse for the x- and y-shift register shifts the pointer individually and makes sure that the sequen tial selection of the lines and columns is correct.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 18 of 48 3.5 temperature reference circuits 3.5.1 temperature diode the most commonly used temperature meas urement is monitoring of the junction voltage of a diode, therefor e we also added a temperature diode to measure the temperature of the silicon di e. this diode junction voltag e is generated by a "small", forward biased, constant current flow (in between 10 and 100 a). this junction voltage has a ne arly linear relationship with the temperature of the die with a typical sensitivity of about 430 c per volt (2.3 mv per c) for silicon junctions. 3.5.2 temperature module on the same image sensor we have fores een a module to verify the temperature on chip and the variation of th e output voltage (dark level of the pixel array) due to a temperature variation. this module contai ns a copy of the complete signal path, including a blind pixel, the column amplifiers and an output stage. it dc response may serve a temperature calibration for the real signal. the temperature functionality is given in figure 7. betw een room temperature and 60 c we see a voltage variation of about 0.5 mv. due to different applied supply voltages, as there are: vreset, vmem, vpix? an offset between the output voltage of the te mperature sensor and the output of a black signal of the pixel array can occur. depending on the working conditions of the image sensor one can fine-tune the temperat ure module with its voltage supply. in case one has a 6v signal for reset and a 4- 6v signal for vmem, a supply voltage of 5.5v for the temperature sensor will result in a closer match between this temperature sensor and the black level of the image se nsor. changing the supply voltage of the temperature sensor results only in a shift of the output voltage therefore the supply voltage of the temperature module can be tuned to make the output of the module equal to the dark signal of the pixel ar ray at a certain working temperature. vsupply (v) 5 5.5 6 6.1 6.2 6.3 6.4 6.5 vout @ 21 c 0.58 0.8 1.03 1.07 1.12 1.17 1.22 1.27
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 19 of 48 0.99 1.01 1.03 1.05 1.07 1.09 1.11 1.13 25 35 45 55 65 75 temperature (c) vout (v) 6 6.1 6.2 figure 7: output voltage of the temp erature module ve rsus temperature
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 20 of 48 3.6 synchronous shutter in a synchronous (snapshot) shutter light in tegration takes place on all pixels in parallel, although subsequent readout is sequential. time axis line number integration time burst readout time common reset common sample&hold flash could occur here figure 8: synchronous shutter operation figure 8 shows the integration and read out sequence for the synchronous shutter. all pixels are light sensitive at the same period of time. th e whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pi xel. the pixel core is re ad out line by line after integration. note that the integration and read out cycle can occur in parallel. i ntegration i + 2 r ead frame i + 1 i ntegration i + 1 r ead frame i figure 9:integration and read out in parallel the control of the readout of the frame and of the integration time are independent of each other with the only exception that the e nd of the integration time from frame i+1 is the beginning of the readout of frame i+1.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 21 of 48 3.7 non-destructive readout (ndr) the sensor can also be read out in a non-de structive way. after a pixel is initially reset, it can be read multiple times, without resetting. the initial reset level and all intermediate signals can be recorded. high light levels will saturate the pixels quickly, but a useful signal is obtained from the early samp les. for low light levels, one has to use the later or latest samples. time figure 10. principle of non-destructive readout. essentially an active pixel array is read multiple times, and reset only once. the external system intelligence takes care of the interpretation of the data. table 6 summarizes the advantages and disadva ntages of non-destructive readout. table 6: advantages an d disadvantages of non-destructive readout. advantages disadvantages low noise ? as it is true cds. sy stem memory required to record the reset level and the intermediate samples. high sensitivity ? as the conversion capacitance is kept rather low. requires multiples read ings of each pixel, thus higher data throughput. high dynamic range ? as the results includes signal for short and long integrations times. requires system level digital calculations. 3.8 operation and signaling one can distinguish the different signals into different groups: ? power supplies and grounds ? biasing and analog signals ? pixel array signals ? digital signals ? test signals
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 22 of 48 3.8.1 power supplies and grounds every module on chip, as there are: column readout, output stages, digital modules, drivers, ? has its own power supply a nd ground. off chip the grounds can be combined, but not all power supplies may be combined. this results in several power supplies, but is required to reduce elect rical crosstalk and to improve shielding. on chip we have the ground lines also separately for every module to improve shielding and electrical crosstalk between them. the only special ground is ?gnd_res?, which can be used to remove the blooming if any and which can improve optical crosstalk. an overview of the supplies is given in table 7. the power supplies related to the pixel array signals are described in the pa ragraph concerning the pixel array signals. note: normal application doesn?t require th is gnd_res and it can be connected to ground. name max curren t typ. max description vdda 50ma 5v power supply column readout module vdd 20ma 5v power s upply digital modules voo 85ma 5v power s upply output stages vstable 6ma 5.5v 6v power supply output stages. decouples noise on the voo supply from the output signal. vpix 200ma 5v 6v power supply pixel array. vddr 20ma 5v power supply logic for drivers vres 50ma 6v power supply to reset the pixels vmemh 50ma 6v power supply for high dc level vmem vmeml 50ma 4.5v power supply for low dc level vmem table 7: power supplies used in the lupa design the maximum currents mentioned in table 7 are peak currents. the power supplies need to be able to deliver these current s especially the maximum supply current for vpix. it is important to notice that we don?t do any power supply filtering on chip and that noise on these power supplies can contribute immediately to the noise on the signal. especially the voltage supplies vpix and v dda are important to be well noise free. with respect to the power supply voo, a special decoupling is used, for which an additional power supply vs table is required.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 23 of 48 important notes: 1.at start up the vpix supply draws a very high current (> 300 ma) which has to be limited (max. 200 ma) otherwise the bond wire s of the particular supply will be destroyed. one should make sure that the vpix power supply limits the current draw to the vpix sensor supply pins to max. 200ma. when the bond wires of vpix are destroyed the sensor isn?t operating normally and will not meet the described specifications. 2. vmeml must sink a current, not source it. all power supplies should be decoupled very close to the sensor pin (typical 100nf to filter high frequenc y dips and 10 microf to filter slow dips). a typical decoupling circuit is s hown in the figure below. vres_ds must be able to sink and source current. figure 11a: schematic of typical decoupl ing of power supply (source current) figure 11b: schematic of typical dec oupling of power supply (sink current)
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 24 of 48 3.8.2 biasing and analog signals besides the biasing signals, the only anal og signals are the output signals out1 ? out16. each output si gnal is analog with respect to the voltage level, but is discrete in time. this means that on the speed of clock_x, the outputs ch ange to a different level, depending on the illuminati on of the corresponding pixels. the biasing signals determine the speed and power dissipation of the different modules on chip. these biasing signals ha ve to be connected trough a resistor to ground or power supply and shoul d be decoupled with a capaci tor. if the sensor is working properly, each of the biasing signals will have a dc-voltage depending on the resistor value and on the internal circuitry. these dc-voltages can be used to check the operation of the image sensor. table 8 gives the different bi asing signals, the way they should be connected, and the expect ed dc-voltage. du e to small process variations, these dc-voltages change from chip to chip and 10% variation is possible. signal comment expected dc- level pre_load connect with 10k ? to vdda and capacitor of 100nf to gnd 2.0v col_load connect with 2m ? to vdda and capacitor of 100nf to gnd 0.9v psf_load connect with 240k ? to gnd and capacitor of 100nf to vdda 3.7v nsf_load connect with 100k ? to vdda and capacitor of 100nf to gnd 1.3v load_out connect with 27k ? to voo and capacitor of 100nf to gnd 1.6v decx_load connect with 27k ? to gnd and capacitor of 100nf to vdd 2.8v decy_load connect with 27k ? to gnd and capacitor of 100nf to vdd 2.8v table 8 : overview of biasing signals each resistor controls the speed and po wer dissipation of th e corresponding module, as this resistor determines the current re quired to charge and/or discharge internal nodes inside the module. a decoupling with a small capacitor is a dvisable to reduce the hf noise onto the analog signals. only the capacitor on the pre_load signal can be omitted. 3.8.3 pixel array signals figure 4 in paragraph 2.2 is a schematic re presentation of the pixel as used in the lupa design. the applied signals to th is pixel are: reset, sample, precharge,
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 25 of 48 vmemory, row select and vpix. these are internal generated si gnals derived by on chip drivers from external a pplied signals. conse quently it is important to understand the relation between both internal and extern al signals and to understand the operation of the pixel. the timing of the pixel is given in figure 12 in which only the internal signals are given. figure 12: internal timing of the pixel. at the end of the integration time, the in formation on the photodiode node needs to be sampled and stored onto the pixel memory, required to allow synchronous shutter. to do this, we need the signals ?precharg e? and ?sample?. ?precharge? resets the pixel memory and ?sample? places the pi xel information onto the pixel memory. once this information stored, the readout of the pixel memories can start in parallel with a new integration time. an additi onal signal ?vmem? is needed to obtain a larger output swing. except from vpix power supply, drivers gene rate the other pixel signals on chip. the external signals to obtain th e required pulses consist of 2 groups. one is the group of digital signals to indicate when the pulse must occur and the other group is dc-supply lines indicating the levels of the pulses. table 9 summarizes the relation between the internal and external pixel array signals internal signal vlow vhigh external control signal low dc level high dc level precharge 0 5v precharge gnd vddr sample 0 5v sample gnd vddr reset 0v 4 ? 6v reset & reset_ds gnd_res vres & vres_ds vmemory 4.5v 6v mem_hl vmem_l vmem_h table 9: overview of the internal and external pixel array signals. the precharge and sample signals are the mo st straightforward si gnals. the internal
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 26 of 48 signal vmemory is a signal that switches between a low voltage (3.5 ? 5.5v) and a high voltage (5-6v). the signal mem_hl c ontrols the applied level and the power supply lines vmem_l and vmem_h determine the low and high dc-levels. the reset signal is due to the dual slope tec hnique a little more complex. in case the dual slope is not used, the reset signal is st raightforward generated from the external reset pulse. in this case the supply volta ge vres determines the level to which the pixel is resetted. in case the dual slope operation is desired, one needs to give a second pulse to a lower reset level during integration. this can be done by the control signal reset_ds and by the power supply vres_ds that defines the level to which th e pixel has to be resetted. if a pulse is given on the rese t_ds signal, a second pulse on the internal reset line is generated to a lower level, determined by the supply vres_ds. if no reset_ds pulse is given, the dual slope technique is not implemented. note that reset is dominant over reset_ds, which means that the high voltage level will be applied for reset, if both pulses occur at the same time. the external control signals should be capa ble of driving input capacitance of about 20pf. 3.8.4 digital signals the digital signals control the readout of the image sensor. these signals are: ? sync_y: starts the readout of the fram e or window at the address defined by the y-address register. this pulse s ynchronizes the y-address register: active high. this signal is at the same tim e the end of the frame or window and determines the window width. ? clock_y: clock of the y-register. on th e rising edge of this clock, the next line is selected. ? sync_x: starts the readout of the selected line at the address defined by the x- address register. this pul se synchronizes the x-addres s register: active high. this signal is at the same time the e nd of the line and determines the window length. ? address: the x- and y-address is dow nloaded serial through this signal. ? clock_spi: clock of the serial paralle l interface. this clock downloads the address into the spi register. ? load_addr: when the spi register is down loaded with the desired address, the signal load_addr signal loads the x-and y-a ddress into their address register as starting point of the wi ndow of interest. ? sh_col: control signal of the column re adout. is only used in sample & hold mode (see timing) ? norow_sel: control signal of the column readout. is only used in norow_sel mode ( see timing) ? pre_col: control signal of the column readout to reduce row blanking time ? sel_active: activates the ac tive load on chip for the out put amplifiers. if not used, a passive load can be used or one can use this signal to put the output
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 27 of 48 stages in standby mode. ? eos_x: end of scan signal: is an output signal, indica ting when the end of the line is reached. is not generated when doing windowing ? eos_y: end of scan signal: is an output signal, indica ting when the end of the frame is reached. is not gene rated when doing windowing. all digital signals are buffere d and filtered on chip to re move spikes and to achieve the required on chip driving speed. the appl ied digital signals should be capable of driving 20pf input capacitance. 3.8.5 test signals some test signals are required to evalua te the optical performance of the image sensor. other test signals allow us to test internal modules in the image sensor and some test signals will give us informati on concerning temperature and influence of the temperature on the black level. evaluation on the optical performan ce (spectral response, fill factor) ? array_diode ? full_diode evaluation of the output stages: ? black ? dc_black evaluation of the x and y ?shift registers: ? eos_x ? eos_y indication of the temperature and influence on the black level: ? temp_diode_n ? temp_diode_p
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 28 of 48 4 timing 4.1 timing of the pixel array the timing of the image sensor can be divided in two major parts. the first part of the timing is related with the timing of the pi xel array. this implies the control of the integration time, the synchronous shutter operation, and the sampling of the pixel information onto the memory element inside each pixel. the signals needed for this control are described in previous paragr aph 3.7.3 and figure 12 shows the timing of the internal signals. figure 13 should make the timing of the external signals clear. figure 13: timing of the pixel array. all external signal s are digital signals between 0 and 5v. the reset_ds is only require d in case dual slope is desired. symbol name value a mem _ hl > 5 sec b mem_hl ?precharge > 200 nsec c precharge > 500 nsec d sample > 3.9 sec e precharge-sample > 400 nsec f integration time > 2 sec table 10: typical timings of the pixel array the timing of the pixel array is straightforward. before the frame is read, the information on the photodiode needs to be st ored onto the memory element inside the pixels. this is done by means of the si gnals vmemory, precharge and sample. precharge sets the memory element to a reference level and sample stores the photodiode information onto the memory elem ent. vmemory pumps up this value to
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 29 of 48 reduce the loss of signal in the pixel and th is signal must be the envelop of precharge and sample. after vmemory is high again, th e readout of the pixel array can start. the frame blanking time or frame overhead ti me is thus the time that vmemory is low, which is about 5 sec. once the readout star ts, the photodiodes can all be initialised by reset for the next integrat ion time. the duration of the reset pulse indicates the integration time fo r the next frame. the longer this duration, the shorter the integration time becomes. maximum integration time is thus the time it takes to readout the frame, minus the minimum pulse for reset, which is preferred not to be less than 10 sec. the minimal integration time is the minimal time between the falling edge of reset and the rising edge of sample. keeping the slow fall times of the corresponding internal generated signals, a minimal integration time is about 2 sec. an additional reset pulse can be given duri ng integration by reset_ds to implement the double slope integration mode . (see paragraph 6.1) 4.2 readout of the pixel array once the photodiode information is stored in to the memory element in each pixel, the total pixel array of 1280 * 1024 needs to be readout in less than 2 msec (2msec ? frame overhead time = 1995 sec). additionally, it is possible that only a part of the whole frame is read out. this is controll ed by the starting address that has to be downloaded and from the end address, whic h is controlled by the synchronisation pulses in x- and y direction. the readout itse lf is straightforward. line by line is selected by means of a sync-pulse and by means of a clock_y signal. once a new line selected, it takes a while (row blanking time) before the information of that line is stable. after this row blanking time the data is multiplexed in blocks of 16 to the output amplifiers. a sync- pulse and a clock pulse in the x-direction do this multiplexing. figure 14 shows the y-address timing. the to p curves are the selection signals of the pixels, which are sequentially active, star ting by the sync pulse. the next line is selected on the rising edge of clock_y. it is important that the sync_y pulse covers 1 rising edge of the clock_y signal. otherwise the sync hronization will not work properly. figure 14 : timing of the y shift register . the first selected line after a sync_y pulse is the line defined by the y-address in the y-address register. every select line is in principle 1 clock period long, except for the
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 30 of 48 first select line. the first select line goes high as soon as a sync_y pulse occurs together with a rising edge of clock_y. on the next rising edge of clock_y, the next row is selected, unless sync_y is still ac tive. in figure 15, a short sync_y pulse makes sure that the first row is sele cted during 1 period of clock_y. once a line is selected, it needs to stabil ize first of all, which is called the row blanking time, and secondly th e pixels need to be read out. figure 15 shows the principle. figure 15: readout time of a line is the sum of the row blanking time and on the line readout time. symbol name value a sync_y > 100 nsec b sync_y-clock_y > 50 nsec c clock_y-sync_y > 50 nsec d sync_x ?clock_x > 50ns once the information of the selected line is stable the addressi ng of the pixels can start. this is done by means of a sync_x and a clock_x pulse in the same way as the y-addressing. the sync_x pu lse downloads the address in the address register into the shift register and connects the first bl ock of 16 columns to the 16 outputs. in fact on chip is a 32-output bus instead of 16, but on the rising edge of clock_x the first 16 columns of the bus are connected to the output stages. on the falling edge of clock_x, the last 16 columns of the selected bus are connected to the output stages.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 31 of 48 figure 16: timing of the x-shift register. the curves from bottom to top : clock_x, sync_x, internal generated clo ck, sel_block1, sel_block2,? the timing in figure 16 is comparable with the timing of the y-shift register, only that the timing is much faster. again the synchr onization pulse must be high on the rising edge of clock_x. important note : the applied clock_x, is filt ered on chip to remove spikes. this is especially required at these high speeds. this filtering results in an on chip clock_x that is delayed in time with about 10nsec. in other words, the data at the output has, with respect to the external clock_x, a propagation de lay of 20nsec. this 20nsec come from 10nsec of the generation of the internal clock_x and 10nsec due to other on chip generated signals. 4.2.1 reduced row overhead time timing the row overhead time is the time between the selection of lines that one has to wait to get the data stable at the column amplifiers. this row overhead time is a loss in time , which should be reduced as much as possible. 4.2.1.1 reduced timing a straightforward way of reduc ing the r.o.t is by using a sample and hold function. by means of sh_col the analog data is tracked during the first 200nsec during the selection of a new set of line s. after 200nsec, the analog da ta is stored. the rot is in this case reduced to 200nsec, but as the internal data was not stable yet dynamic range is lost because not the complete analog levels are reached yet after 200ns. figure 17 shows this principle. sh_col is now a pulse of 100ns-200ns starting 25 ns after norowsel. the duration of sh_col is equal to the rot. the shorter this time the shorter the rot will be however th is lowers also the dynamic range.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 32 of 48 figure 17: reduced standard rot by means of sh_col signal. pre_col (short pulse) , norowsel (short pulse) and sh_col (large pulse). 4.2.1.2 standard timing (rot = 200 ns) figure 18: only pre_col and no rowsel control si gnals are required. sh_col is made active low. in this case the control signals norowsel and pre_col are made active for about 50 nsec from the moment the next line is se lected. the time these pulses have to be active is related with the biasing resistance pre_load. the lower this resistance, the shorter the pulse duration of norowsel an d pre_col may be. after these pulses are given, one has to wait for 180nsec before th e first pixels can be sampled. for this mode sh_col must be made active low.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 33 of 48 4.3 timing of the serial parallel interface (spi) the serial parallel interface is used to upload the x- and y-address into the x- and y- address registers. this address is the star ting point of the window of interest and is uploaded in the shift register by means of the corresponding sync hronization pulse. the elementary unit cell of the serial to parallel interface is shown in figure 19. 16 of these cells are connected in parallel, having a common load_a ddr and clock_spi form the entire uploadable address block. the uploaded addresses are applied to the sensor on the rising edge of signal load_addr. d q c d q c address_in to address registers address_out clock_spi load_address 16 outputs to sensor : 6 x-a dd ress bits and 10 y-address bits clock_spi address unity cell entire uploadable address block load_addr a1 a2 a3 a16 load_addr clock_spi address command applied to sensor figure 19: schematic of the spi interface the y-address has to be applied first and the x-address last. with respect to the timing in figure 19, a1 corresponds with th e least significant bit of the y-address (y0) and a16 corresponds with the most signi ficant bit of the x- address (x5). the y-address is a 10 bit and the x-a ddress is a 6-bit address register .
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 34 of 48 5 pin configuration the LUPA-1300 sensor will be packed in a pga package with 145 pins. each bond pad consists of 2 pad openings, one for wa fer probing and one for bonding. table 11 gives an overview of the pin na mes and their functionality. pin fp name function description b3 1 n.c. not connected c3 2 n.c. d3 3 voo supply 5v supply voltage output stages : 5v a2 4 gnd ground ground of the sensor b2 5 out1 analog out output 1 e3 6 voo supply 5v supply voltage output stages : 5v c2 7 out2 analog out output 2 d2 8 gnd ground ground of the sensor e2 9 out3 analog out output 3 a1 10 voo supply 5v supply voltage output stages : 5v f3 11 out4 analog out output 4 f2 12 gnd ground ground of the sensor b1 13 out5 analog out output 5 c1 14 voo supply 5v supply voltage output stages : 5v d1 15 out6 analog out output 6 g3 16 gnd ground ground of the sensor e1 17 out7 analog out output 7 g2 18 voo supply 5v supply voltage output stages : 5v f1 19 out8 analog out output 8 g1 20 gnd ground ground of the sensor h3 21 out9 analog out output 9 h2 22 voo supply 5v supply volta ge output stages : 5v h1 23 out10 analog out output 10 j1 24 gnd ground ground of the sensor j2 25 out11 analog out output 11 j3 26 voo supply 5v supply volta ge output stages : 5v k1 27 out12 analog out output 12 k2 28 gnd ground ground of the sensor l1 29 out13 analog out output 13 k3 30 voo supply 5v supply volta ge output stages : 5v l2 31 out14 analog out output 14 m1 32 gnd ground ground of the sensor n1 33 out15 analog out output 15 l3 34 voo supply 5v supply volta ge output stages : 5v m2 35 out16 analog out output 16
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 35 of 48 p1 36 gnd ground ground of the sensor n2 37 voo supply 5v supply volta ge output stages : 5v m3 38 n.c. p2 39 n.c. n3 40 gnd ground ground of the sensor n4 41 voo supply 5v supply volta ge output stages : 5v n5 42 vstable supply 5v supply voltage to stabilize output stages : 5.5v p3 43 load_out biasing analog bias for output amplifiers 27k ? to voo and capacitor of 100nf to ground p5 44 dc_black testpin 6 dc-b lack signal required to characterise the output stages p4 45 vdd supply 5v supply volta ge digital modules : 5v q1 46 gnd ground ground of the sensor n6 47 vdda supply 5v supply vo ltage analog modules : 5v p6 48 gnd ground ground of the sensor q2 49 vpix supply 5v supply voltage pixel array : 5v q3 50 eos_x digital i/o end of scan si gnal of the x-register : active high pulse indicates the end of the shift register is reached q4 51 nsf_load biasing analog bias for column stages : 100k ? to vdda and capacitor of 100nf to ground n7 52 psf_load biasing analog bias for column stages : 240k ? to gnd and capacitor of 100nf to vdda p7 53 col_load biasing analog bias for column stages : 2m ? to vdda and capacitor of 100nf to ground q5 54 pre_load biasing analog bias for column stages : 10k ? to vdda and capacitor of 100nf to ground q6 55 n.c. q7 56 array_diode testpin 3 array of pi xels as designed in pixel array n8 57 full_diode testpin 4 full diode wi th same array as array diode : 140 * 70 m 2 p8 58 temp_diode_p testpin 1 te mperature diode p side q8 59 temp_diode_n testpin 2 te mperature diode n side q9 60 n.c. p9 61 n.c. n9 62 n.c. q10 63 n.c. q11 64 n.c. q12 65 n.c. p10 66 n.c. n10 67 n.c. q13 68 n.c. p11 69 vpix supply 5v supply voltage pixel array : 5v
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 36 of 48 p12 70 gnd ground ground of the sensor n11 71 vddr supply 5v supply voltage of the logic for the drivers : 5v n12 72 n.c. p13 73 vmem_l supply voltage supply for vmemory drivers : 3v- 5v (typ: 4.5v) n13 74 vmem_h supply voltage supply for vmemory drivers : 4v- 6v (typ. 6v) m13 75 vres_ds supply voltage supply for reset double sloped drivers : 4v ? 5v q14 76 vres supply voltage supply for reset drivers : 5v ? 6v (typ 6v) p14 77 gnd_res ground_ab ground anti-blooming : 0 ? 1v l13 78 n.c. n14 79 n.c. m14 80 n.c. l14 81 n.c. q15 82 n.c. k13 83 n.c. k14 84 n.c. p15 85 n.c. n15 86 n.c. m15 87 n.c. j13 88 n.c. l15 89 n.c. j14 90 n.c. k15 91 n.c. j15 92 n.c. h13 93 n.c. h14 94 gnd ground ground for temperature module h15 95 temp testpin 5 dark level si gnal as function of temperature (figure 7) g15 96 vdd supply supply voltage temperature module : 5v (has to be tunable to adjust output of temperature module to analog output) g14 97 n.c. g13 98 n.c. f15 99 n.c. f14 100 n.c. e15 101 reset_ds digital i/o double slope reset of the pixels: active high pulse f13 102 reset digital i/o reset signal of the pixels : active high pulse e14 103 mem_hl digital i/o control of vmemory signal : 5v: vmem_h, 0v : vmem_l
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 37 of 48 d15 104 sample digital i/o samples the photodiode voltage onto the memory cell inside each pixel : active high pulse c15 105 precharge digital i/o precharge th e memory cell inside the pixel : active high pulse e13 106 eos_y digital i/o end of scan si gnal of the y-register : active high pulse indicates the end of the shift register is reached d14 107 gnd_res ground_ab ground for the reset drivers. can be used as anti-blooming by applying 1v instead of 0v b15 108 vres supply voltage supply for reset drivers : 5v ? 6v (typ: 6v) c14 109 vres_ds supply voltage supply for reset double sloped drivers : 4v ? 5v d13 110 vmem_h supply voltage supply for vmemory drivers : 5v- 6v (typ: 6v) b14 111 vmem_l supply voltage supply for vmemory drivers : 3v- 5v (typ: 4.5v) c13 112 vddr supply 5v supply voltage of the logic for the drivers : 5v c12 113 vpix supply 5v supply voltage pixel array : 5v c11 114 vdd supply 5v supply volta ge digital modules : 5v b13 115 gnd ground ground of the sensor b11 116 n.c. b12 117 n.c. a15 118 n.c. c10 119 n.c. b10 120 n.c. a14 121 n.c. a13 122 n.c. a12 123 n.c. c9 124 n.c. b9 125 n.c. a11 126 load_addr digital i/o loads the a ddress into the serial parallel interface (spi) a10 127 address digital i/o serial addres s to be downloaded into the spi a9 128 clock_spi digital i/o clock for the spi c8 129 decy_load digital i/o bias for y address register : 27k ? to ground and capacitor of 100nf to vdd b8 130 sync_y digital i/o synchronisation of y-address register : active high a8 131 clock_y digital i/o clock of y-address register a7 132 norow_sel digital i/o control signa l for norow_sel mode to reduce row blanking time : active low
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 38 of 48 b7 133 sh_col digital i/o control signal for sh_col mode to reduce row blanking time : active low (baseline method) : active low c7 134 pre_col digital i/o additional c ontrol signal for reducing the row blanking time a6 135 sync_x digital i/o synchronisation of the x-address register : active high a5 136 clock_x digital i/o clock of the x-address register a4 137 decx_load biasing bias for x address register : 27k ? to ground and capacitor of 100nf to vdd b6 138 black digital i/o controls blac k test function of the output stages : active high c6 139 sel_active digital i/o set the output stages active or in standby mode : active low a3 140 vdd supply 5v supply volta ge digital modules : 5v b5 141 gnd ground ground of the sensor b4 142 vdda supply 5v supply vo ltage analog modules : 5v c5 143 gnd ground ground of the sensor c4 144 voo supply 5v supply voltage output stages : 5v table 11 : pin description of the assembled LUPA-1300 sensor in the pga 144 package.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 39 of 48 6 pad positioning and packaging 6.1 package a b c d e f g h j k l m n p q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 25,62 1 9,5 40,01 40,01 r 1 , 2 7 b d et ai l b scale 4/1 r 1 , 2 7 0,90 0,90 c d et ai l c scal e 4/ 1 23,5 0,25 1 ,02 0,51 2,80 s e c ti o n a -a ' a a' 2,54 35,56 not e 1 ~ not e: 1 . di e at t ach ar ea shoul d be m et al l i zed and connected to pad num ber d 4 al l di m ensi ons i n m m ? 1 , 7 8 29,62 1 ,27 4,57 0,20 4 x 0,5 r 1 1 7,5 23,62 figure 20: package drawi ng of the LUPA-1300 sensor
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 40 of 48 6.2 package and die figure 21: package drawing wi th die of the LUPA-1300 sensor the center of the pixel array is located 200 m to the right and 51 m above the center of the package. the first pixel is lo cated at 9160 m to the left and 7219 to the bottom from this center. all distan ces are with a deviation of 50 m.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 41 of 48 6.3 color filter an optional color filter ca n be processed as well. the LUPA-1300 can also be processed with a bayer rgb color pattern. pixel (0,0) has a red filter. figure 22: color filter arrangement on the pixels.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 42 of 48 6.4 glass transmittance 6.4.1 monochrome a d263 glass will be used as prot ection glass lid on top of the LUPA-1300 monochrome sensors. figure 23 shows the tr ansmission character istics of the d263 glass. 0 10 20 30 40 50 60 70 80 90 10 0 400 500 600 700 800 900 wavelength [nm] transmission [%] figure 23: transmission characte ristics of the d263 glass us ed as protective cover for the ibis5a-1300 sensors. 6.4.2 color for color devices a near infrared attenuating color filter glass is used. the dominant wavelength is around 490 nm. figure 24 shows the transmittance curve for the glass. a s8612 glass will be used as nir cut- off filter on top of the LUPA-1300-c color image sensor. figure 24 shows the transm ission characteristics of the s8612 glass.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 43 of 48 figure 24: transmission charact eristics of the s8612 glass us ed as nir cut-off filter. 6.5 handling and storage precautions 6.6 handling precautions special care should be given when soldering image sensors with color filter arrays (rgb color filters), onto a circuit board, since color filters are sensitive to high temperatures. prolonged heatin g at elevated temperatures may result in deterioration of the performance of the sensor. the foll owing recommendations are made to ensure that sensor performance is not compromise d during end-users? assembly processes. board assembly: device placement onto boards should be done in accordance with strict esd controls for class 0, jesd22 human body model, and class a, jesd22 machine model devices. assembly operators should alwa ys wear all designated and approved grounding equipment; grounded wrist straps at esd protected workstations are recommended including the use of ioni zed blowers. all t ools should be esd protected. manual soldering: when a soldering iron is used the fo llowing conditions s hould be observed: use a soldering iron with temperature control at the tip.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 44 of 48 the soldering iron tip temperature should not exceed 350 c. the soldering period for each pin should be less than 5 seconds. precautions and cleaning: avoid spilling solder flux on the cover glass; bare glass and particularly glass with antireflection filters may be adversely af fected by the flux. avoid mechanical or particulate damage to the cover glass. it is recommended that isopropyl alcohol (ipa) be used as a solvent for cleaning the image sensor glass lid. when using other solvents, it should be confirmed beforehand whether the solvent will dissolve the package and/or the glass lid or not. 6.7 storage conditions description minimum maximum units conditions temperature -10 66 c @ 15% rh temperature -10 38 c @ 86% rh note: rh = relative humidity 7 ordering information fillfactory part number cypress semiconductor part number LUPA-1300-c cyil1sc1300aa-gac LUPA-1300-m cyil1sm1300aa-gbc disclaimer fillfactory image sensors are only warranted to meet the specifications as described in the data sheet. specifications are subject to change without notice.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 45 of 48 8 application notes & faq q: can the LUPA-1300 directly drive an adc? a: yes, coupling the LUPA-1300 to a set of 16 adc?s close to the chip is the preferred way of operation. a suitable adc must have thus ? input range equal or larger than the 1.2 v- 0 v sensor signal swing ? in view of the LUPA-1300?s s/n 10 bits are suitable. 11 or 12 bits may be considered too. ? input capacitance 20 pf or lower (high output loads will limit the speed). and no significant resi stive loading. ? sampling frequency 40 mhz (or the a pplication specific sample rate) ? the adc?s input bandwidth must be sufficiently higher than the sampling frequency, in order to avoid rc cont amination between successive pixels. q: how does the dual slope exte nded dynamic range mode works? a: figure 25: dual slope diagram the green lines are the analog signal on th e photodiode, which decrease as a result of exposure. the slope is determined by the amount of light at each pixel (the more light the steeper the slope). when the pixels reach the saturation level the analog signal will not change despite further exposure. as you can see without any double slope pulse pixels p3 and p4 will reach saturation before the sample moment of the analog p 4 p3 p2 p 1 r ese t level 1 r eset level 2 saturation level total integration time r eset pulse d ouble slope reset pulse r ead out double slope reset time (usually 5-10% of the total integration time)
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 46 of 48 values, no signal will be acquired without double slope. when double slope is enabled a second reset pulse will be given (blue line ) at a certain time before the end of the integration time. this double slope reset pul se resets the analog signal of the pixels below this level to the reset level. after the reset the analog signal starts to decrease with the same slope as before the double slope reset pulse. if the double slope reset pulse is placed at the end of th e integration time (90% for instance) the analog signal that would have reach the sa turation levels aren't saturated anymore (this increases the optical dynamic range) at read out. it's important to notice that pixel signals above the double slope re set level will not be influenced by this double slope reset pulse (p1 and p2). please look at our website to find some pictures taken with the double slope mode on: http://www.fi llfactory.be/htm/technol ogy/htm/dual-slope.htm
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 47 of 48 appendix a: LUPA-1300 evaluation kit for evaluating purposes a LUPA-1300 evaluation kit is available. the LUPA-1300 evaluation kit co nsists of a multifunctiona l digital board (memory, sequencer and ieee 1394 fire wire interface), an adc-board and an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images and movies from the sensor. all ac quired images and movies can be stored in different file formats (8 or 16-bit). all sett ing can be adjusted on the fly to evaluate the sensors specs. default register values can be loaded to start the software in a desired state. please contact fillfactory ( info@fillfactory.com ) if you want any more information on the evaluation kit.
LUPA-1300 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document # : 38-05711 rev.**( revision 3.1) page 48 of 48 document history page document title: LUPA-1300 1.3m high speed cmos image sensor document number: 38-05711 rev. ecn no. issue date orig. of change description of change ** 310396 see ecn sil initial cypress release (eod)

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